In semiconductor memories, redundancy refers to the complexity of circuits and additional memory elements provided in the memory device to "repair" defective memory elements. By means of redundancy, a memory device affected by at most a limited number of defects can be recovered.
Redundancy memory elements are formed by memory cells identical to the memory cells of the memory matrix, and are arranged in rows (redundancy row) or columns (redundancy columns). The redundancy circuits control the selection of a given redundancy row or redundancy column in substitution for a defective row or column of the memory matrix, i.e., a row or column in which at least one defective memory cell is detected. To this purpose, the redundancy circuits comprise non-volatile memory registers to store addresses of the defective rows or columns, so that when the defective rows or columns are accessed (during reading or programming) they are not selected, and the corresponding redundancy rows or redundancy columns are instead selected.
The provision of redundancy in a memory device clearly has a cost in terms of chip area. The number of redundancy memory elements (redundancy rows or columns) to be provided must be evaluated on the basis of the overall yield, taking into account the degree of defectivity of the manufacturing process and the number of defective memory device chips which can be recovered thanks to the provision of redundancy.
The functional substitution of defective rows or columns with redundancy ones is performed during the in-factory testing of the memory device, and is normally transparent to the end user.
It is useful to have the possibility of testing the redundancy circuits. This is necessary to verify the complete functionality of the redundancy circuits, for example to ascertain that the non-volatile memory registers which must store the defective addresses are free of errors. Testing of the redundancy circuits is also necessary to extrapolate statistic informations on the degree of defectivity of the manufacturing process, so that the number of redundancy memory elements can be adjusted to attain the maximum process yield.